This invention relates to a semiconductor integrated circuit arrangement in which the photo leakage current caused by incident light is decreased vis-vis conventional arrangements.
The fewer external terminals on an integrated circuit the better FIG. 1 illustrates a prior art circuit which is arranged so as to have a minimum number of external terminals. Terminal 10 is connected to a drain and gate of an enhanced type of MOS transistor T10. A source of transistor T10 is connected to a node A, and node A receives an electric potential V.sub.c through a source and drain of a depletion type MOS transistor T12. Node A is also connected to a node D through a drain and source of a depletion type MOS transistor T14. A gate of transistor T14 is connected to node D, and node D is also connected to an electric potential V.sub.s through a drain and source of an enhancement type MOS transistor T16. Potential Vs is usually the same potential as the semiconductor substrate, for example zero.
A gate terminal B of transistor T12 is maintained at logic "1", namely potential V.sub.c (for example, 5 volts), when terminal 10 receives a signal OE which is normally zero. If the potential of node A is V.sub.c and the gate threshold voltage of transistor T10 is V.sub.th10, transistor T10 is cut off and node A is electrically separated from terminal 10 when the relation OE.ltoreq.V.sub.c +V.sub.th10 exists. At this time, a signal having a potential zero or V.sub.c is produced on node D responding to the logic level of gate terminal C of transistor T16.
Gate terminal B shifts into logic state "0" when terminal 10 receives signal V.sub.p. If the gate threshold voltage of transistor T12 is V.sub.th12 and the potential of gate terminal B is V.sub.GB, transistor T12 is cut off when the relations V.sub.p -V.sub.th10 24 V.sub.GB -V.sub.th12 and V.sub.c .gtoreq.V.sub.GB -V.sub.th12 are satisfied. As a result, the potential of node D is V.sub.p -V.sub.th10 when gate terminal C of transistor T16 is at logic "0", and is zero when gate terminal C is at logic "1".
Transistor 10 is operated "on" or "off" responding to the potential differences between node A and terminal 10 in the circuit shown in FIG. 1, and terminal 10 is used as the terminal for two kinds of signals V.sub.p and OE.
Transistor T10 is cut off when terminal 10 is used as the terminal for signal OE. Therefore, the fan-out of another circuit connected to terminal 10 is not decreased by the circuit current of node A. In general for a MOS-integrated circuit, the current upper limit of the signal input circuit, namely the current capacity, is nearly .+-.10 micro amperes (.mu.A). Accordingly, the leakage current from terminal 10 to node A or from node A to terminal 10 should be sufficiently smaller than this current capacity. If transistor T10 is completely cut off, the leakage current must be very small. However, the leakage current cannot be bypassed if light is irradiated on the P-N junction of transistor T10 during its operation.
An ultraviolet ray erasable type EPROM (Erasable Programmable Read Only Memory) is a semiconductor device in which junctions in the integrated circuit are irradiated during operation. EPROMS have been placed in light passing packages having a window provided above the integrated circuit chip for passage of ultraviolet rays. In use, P-N junctions of the integrated circuit including transistor T10 (shown in FIG. 1) receive the light and the junction photo leakage currents produced by the light flow to terminal 10.
FIG. 2 is a graphical representation illustrating the relation between the junction photo leakage current and the illumination of the irradiating light. FIG. 3 illustrates a measuring circuit for FIG. 2. Referring to FIG. 2, the reverse bias voltage V.sub.D of the P-N junction is represented by a solid line of V.sub.D =8 volts and a dotted line of V.sub.D =0 volts. FIG. 2 illustrates leakage current I.sub.L per light receiving area .mu.m.sup.2. When the illumination is intense, the total of the leakage current I.sub.L cannot be bypassed in a semiconductor device having a large light receiving area such as an EPROM. For example a 32K bit EPROM has a substantial light receiving area of nearly 1.5.times.10.sup.5 .mu.m.sup.2. In this case, when the illumination is 3000 lux, photo leakage current I.sub.L is 4.times.10.sup.-11 (A/.mu.m.sup.2), and total leakage currents are EQU 1.5.times.10.sup.5 .times.4.times.10.sup.-11 =6.times.10.sup.-6 (A)=6(.mu.A)
A leakage current of 6 .mu.A cannot be bypassed to the abovementioned current capacity (.+-.10 .mu.A). Consequently, there is the possibility that the circuit will not operate normally if the EPROM is used under a bright light.
FIG. 4 illustrates a partial circuit of the EPROM of FIG. 1. A V.sub.p voltage detecting circuit 12 is used to distinguish whether the input signal of terminal 10 is V.sub.p or OE, and is constructed as a kind of level comparator. When the potential of terminal 10 is less than V.sub.c (5 volts) a node E is at logic "1"; when it is V.sub.p (25 volts) node E is at logic "0". Node E is connected to the gates of depletion type MOS-transistors T18a to T18n and gate terminals B and C. V.sub.p voltage detecting circuit 12 turns on and off transistors T12, T16 and T18a to T18n responding to the potential of terminal 10. Transistors T18a to T18n are gating transistors inserted between column or row decoders 14a to 14n and decoder output lines 16a to 16n.
Node D is connected to the gates of enhancement type MOS transistors T20a to T20n. All drains of transistors T20a to T20n are connected to terminal 10. Each source of transistors T20a to T20n is connected to decoder output lines 16a to 16n through depletion type MOS-transistors T22a to T22n. The decoder output lines are constructed by 256 lines as columns and 16 lines as rows in the memory cells of 8 bit units and 256 columns and 16 rows. Each decoder output line of 256 and 16 lines is respectively connected to a transistor like one of transistors T20 connected to terminal 10. If the P-N junctions of these many transistors are irradiated, the abovementioned bad influences are caused by the resulting large photo leakage currents.
FIGS. 5(a) to (c) illustrate partial constructions of conventional semiconductor devices. FIGS. 5(a) and (b) illustrate the wiring patterns, namely electric conducting layers 50 on contacting holes 48 of the N.sup.+ regions, for example, of drain regions 42. FIG. 5(c) is a section of FIG. 5(a). It is well known to persons skilled in the art that the width of an electric conducting layer 50 has to be narrowed as far as possible to increase integration density. Therefore, most of the P-N junction formed between N.sup.+ type drain region 42 and P type substrate 40 is not covered by electric conducting layer 50. Most of the portions of drain region 42 and substrate 40 are covered by SiO.sub.2 film 44 which passes light, so if electric conducting layer 50 is formed of aluminium to block light, most of the P-N junction will not be irradiated.
If photons having energies irradiate drain region 42, the irradiated energy causes valence band electrons to be excited the conduction band. Consequently, photo leakage currents flow to electric conducting layer 50. Photo leakage currents are produced even at the P-N junction into substrate 40 when photon energies are strong. The conventional constructions shown in FIG. 5 produce large photo leakage currents in response to illumination.